Dynamic Random Access Memory (DRAM), either as an embedded DRAM or as a stand-alone DRAM, is widely used in a variety of applications because the density of the memory (the number of bits that can be stored in the memory per mm2) is the highest of all semiconductor memory technologies. A typical large DRAM memory has blocks of memory cells, the cells disposed in rows and columns within each block. A typical DRAM memory cell comprises a storage capacitor and an access transistor. The capacitor stores a charge related to the value of the data stored in the cell and the access transistor selectively couples the storage capacitor to a column conductor (also referred to as a “bit line”) for reading and writing the memory cell. Because of various leakage paths, the charge on the storage capacitor will typically dissipate in less than a few tens of milliseconds. To maintain integrity of the data in the memory, each cell is periodically “refreshed” to maintain the data therein by reading the data in the memory cell and rewriting the read (“refreshed”) data back into the cell before a charge stored in the storage capacitor has had the opportunity to dissipate. Because of the large number of memory cells (e.g., 16 million) and the row-column structure of the memory, a typical DRAM is designed to refresh all the memory cells in a row at a time. This is known as a row-only or row-by-row refresh, where the entire memory is refreshed by sequencing through all the rows in the memory.
DRAM manufacturers typically specify a maximum interval between refreshes of any row and the interval is same for all rows. The interval is set short enough (typically less than a millisecond) to assure that the “weak” cells in the memory (i.e., those cells with the highest leakage rates, compared to the other (“normal”) memory cells in the DRAM, for all operating temperature and power supply voltage conditions) will not lose any data stored therein. Usually, the length of the refresh interval is based upon a small percentage of the memory cells and is much shorter than necessary for the majority of memory cells in the memory. For one exemplary DRAM, if all the memory cells are refreshed every 100 microseconds, none of the memory cells will fail (i.e., lose data). If, however, the refresh interval is lengthened to one millisecond, then some of the memory cells will fail. Thus in this example, the memory is refreshed every 0.1 milliseconds so that the memory does not lose any of the data stored therein, resulting in a much higher refresh rate than required for the majority of memory cells. The high refresh rate results in relatively high refresh power consumption. Battery operated electronic devices, such as cell phones and multimedia players, require as low as possible power consumption by the memories therein to prolong battery life. Because these applications do not read or write (access) the memory most of the time, very low memory standby power is desirable. A major component of memory standby power is the refresh power. Thus it is desirable to reduce refresh power to very low levels.
One approach reducing refresh power is to replace the memory elements (e.g., whole rows or columns or entire memory blocks) having the weak cells with spare memory elements having no weak cells, and the memory is refreshed using a lower refresh rate than would otherwise be required. Having spare memory elements adds additional silicon area, and therefore cost, to the DRAM.
Another approach is to use error correction techniques (ECC) to correct erroneous data from failing cells while using a lower refresh rate than would otherwise be required. This requires additional circuitry and memory cells (ECC cells) to be added to the memory, increasing silicon area and, thus, cost. In addition, ECC may require extra time during memory reads to detect and correct errors and during memory writes to calculate the ECC data, as well as increasing power consumption during read and write cycles of the memory.